How to define and initialize a vector containing only ones in Verilog?

As a quick simulation would prove, assign mywire = 128'b1; does not assign all bits of mywire to 1. Only bit 0 is assigned 1.

Both of the following always assign all 128 bits to 1:

assign mywire = >; assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

One advantage of the 1st line is that it is more easily scalable to widths greater than and less than 128.

With SystemVerilog, the following syntax also always assigns all 128 bits to 1:

assign mywire = '1;

answered Sep 30, 2013 at 23:56 61.1k 19 19 gold badges 78 78 silver badges 122 122 bronze badges

I would use the following statement instead:

assign mywire = ~0;

in a simple expression like this, the width on the left-hand side of the assignment sets the width for the expression on the right hand side. So 0 , which is a 32 bit constant, is first extended to the full 128 bit of mywire, then all the bits are flipped and the resulting all-ones vector is assigned.

I'd prefer this version because it does not require you to specify the width of mywire anywhere in the assignment.